Mixed-mode mixed-signal 32-bit enhanced version of SPICE2G6 with built-in logic simulator, analog behavioral modeling extensions, PSpicetm and HSPICEtm compatible syntax extensions and many other enhancements. Circuit size is limited only by available system RAM memory.
Input/Output File
TopSPICE input format is an ASCII text file using
the Berkeley SPICE2G6 syntax with extensions for digital simulation and
behavioral modeling. TopSPICE also accepts many PSpicetm, HSPICEtm and
SPICE3 syntax extensions. Output is an ASCII text file in SPICE2G6 format.
The simulation results can also be saved as a compact binary data file.
Analyses
DC operating bias point, DC sweep, AC (frequency) response,
transient response, noise, distortion, Fourier, transfer function, sensitivity,
temperature and parametric stepping, "alter" circuit, Monte Carlo and worst case.
| Command | Description |
|---|---|
| .AC | AC analysis (frequency sweep) |
| .ALTER | Repeat run with altered components |
| .DC | DC sweep |
| .DISTO | Distortion analysis |
| .END | End of circuit |
| .ENDL | End of library entry section |
| .ENDS | End of subcircuit definition block |
| .ENDM | End of macromodel definition block |
| .FOUR | Fourier harmonic analysis |
| .GLOBAL | Global nodes |
| .HSPICE$ | Enable HSPICE in-line comment marker " $" |
| .IC | Initial condition |
| .INC | Include file |
| .LIB | Model library file |
| .LOADBIAS | Load bias point data file |
| .MACRO | Start macromodel definition block |
| .MC | Monte Carlo analysis |
| .MODEL | Device model definition |
| .NODESET | Set node initial voltages |
| .NOISE | Noise analysis |
| .OP | DC operating point |
| .OPTIONS | Set simulator options |
| .PARAM | Define user parameters |
| .PLOT | ASCII "line printer" plot |
| Print tabulated simulation data | |
| .PROBE | Save simulation results to binary data file |
| .RENUMBER | Renumber element reference names |
| .SAVE | Save simulation results to binary data file |
| .SAVEBIAS | Save bias point data to file |
| .SENS | Sensitivity analysis |
| .STAT | Device statistical distribution |
| .STEP | Parametric stepping |
| .SUBCKT | Start subcircuit definition block |
| .TEMP | Set operating temperature and repeat run |
| .TF | DC small-signal transfer function calculation |
| .TRAN | Transient analysis |
| .WC | Worst case analysis |
| .WIDTH | Input/output file line width |
Built-in Circuit Elements
Resistors, capacitors, inductors, coupled
inductors, nonlinear magnetic cores, switches, diodes (model levels 1 and 3), BJTs,
JFETs, MOSFETs (model levels 1, 2, 3, 7, 8, 44, 49, 53, 55),
GaAs FETs (model levels 1, 2, 3 and 6), ferroelectric
capacitors, ideal and lossy transmission lines, voltage and
current sources, controlled sources, digital elements, analog/digital
interfaces, and subcircuits (macromodels).
| Device | Description |
|---|---|
| B | GaAs FET (GASFET) |
| C | Capacitor (linear, ABM expression, POLY, TABLE, PWL, FERRO) |
| D | Diode |
| E | Voltage-controlled voltage source (linear, POLY, VALUE, TABLE, FREQ, LAPLACE, ADD, DIVIDE, MULTIPLY, POWER) |
| F | Current-controlled current source (linear, POLY) |
| G | Voltage-controlled current source (linear, POLY, VALUE, TABLE, FREQ, LAPLACE, ADD, DIVIDE, MULTIPLY, POWER) |
| H | Current-controlled voltage source (linear, POLY) |
| I | Independent current source (AM, EXP, FILE, PULSE, PWL, RANDOM, SFAM, SFFM, SIN) |
| J | JFET, GASFET and MESFET |
| K | Mutual (coupled) inductance, saturable magnetic core |
| L | Inductor (linear, POLY, PWL, saturable core) |
| M | MOSFET |
| O | Analog/digital interface |
| Q | BJT (bipolar transistor) |
| R | Resistor (linear, ABM expression) |
| S | Switch (voltage controlled) |
| T | Transmission line (ideal, LTRA, TRN) |
| U | Digital (logic) element |
| V | Independent voltage source (AM, EXP, FILE, PULSE, PWL, RANDOM, SFAM, SFFM, SIN) |
| X | Subcircuit |
| Z | MESFET (NMF, PMF) |
| Model | Description |
|---|---|
| ATOD | Analog-to-digital interface |
| C | Integrated capacitor |
| CAP | Capacitor |
| CORE | Nonlinear magnetic core (Jiles-Atherton model) |
| D | Diode (levels 1 and 3) |
| DTOA | Digital-to-analog interface |
| FECAP | Ferroelectric capacitor |
| GASFET | GaAs FET (levels 1, 2, 3, 6) |
| HNPN | NPN HBT (heterojunction BJT) |
| HPNP | PNP HBT (heterojunction BJT) |
| LNPN | Lateral NPN BJT |
| LTRA | Lossy transmission line |
| NJF | N-channel JFET |
| NMF | N-channel MESFET |
| NMOS | N-channel MOSFET (levels 1, 2, 3, 7, 8, 44, 49, 53, 55) |
| NPN | NPN BJT |
| PJF | P-channel JFET |
| PMF | P-channel MEFSET |
| PMOS | P-channel MOSFET (levels 1, 2, 3, 7, 8, 44, 49, 53, 55) |
| PNP | PNP BJT |
| R | Integrated resistor |
| RES | Resistor |
| SW | Switch - voltage-controlled |
| TRN | Lossy transmission line |
| U3GATE | Digital tri-state gate |
| UALU | Digital ALU function |
| UCOUNT | Digital counter function |
| UEFF | Digital edge-triggered flip-flop |
| UGATE | Digital gate |
| UGFF | Digital gated flip-flop |
| UIO | Analog/digital interface |
| UPULSE | Digital pulse generator |
| URAM | Digital RAM |
| UROM | Digital ROM |
| USEL | Digital decoders, encoders and multiplexers |
| USREG | Digital shift register |
| USTIM | Digital stimulus generator |
| VSWITCH | Switch - voltage-controlled (levels 0 and 1) |
Analog Behavioral Modeling
POLY (polynomial functions of voltage and
current), VALUE (arbitrary expressions of voltage, current, time and temperature),
TABLE (look-up tables), FREQ (frequency response and s-parameter tables), LAPLACE
(Laplace transforms).
Digital Simulation
Built-in event-driven logic simulator; SPICE
like syntax for logic elements; nine-state logic simulation; separate analog
and digital time step control; no limitations in analog/digital connections;
user specified gate delays; user specified A/D interface models; glitch
and race condition detection; digital state and waveform output options.
Digital Primitives
| Function | Description |
|---|---|
| ADD | N-bit full adder |
| AND | N-input AND gate |
| BUF | Buffer gate(s) |
| BUF3 | Tri-state buffer gate(s) |
| COMP | N-bit magnitude comparator |
| COUNT | N-bit universal counter |
| DEC | N-bit to N-line decoder |
| DFF | Edge-triggered D flip-flop |
| DIVN | Divide-by-N counter |
| DLATCH | Gated D flip-flop (latch) |
| INV | Inverter gate(s) |
| JKFF | Edge-triggered JK flip-flop |
| MUX | One of n-bit multiplexer |
| NAND | N-input NAND gate |
| NOR | N-input NOR gate |
| OR | N-input OR gate |
| PARITY | N-bit parity generator/checker |
| PENC | N-line priority encoder |
| PSREG | N-bit universal shift register (parallel load) |
| PULSE | Pulse generator/multivibrator |
| RAM | Static random-access-memory |
| ROM | Read-only-memory |
| RSFF | Gated RS flip-flop |
| SREG | N-bit shift register (serial in/parallel out) |
| SREGP | N-bit shift register (parallel in/serial out) |
| XNOR | N-input XNOR gate |
| XOR | N-input XOR gate |
Signal Sources:
AM (amplitude modulated), EXP (exponential), FILE (data file), PULSE (pulsed waveform),
PWL (piecewise linear), RANDOM (random waveform), SFAM (single-frequency AM),
SFFM (single-frequency FM), SIN (sine),
CLOCK (digital), DATA (digital). Any arbitrary function in time or frequency
may also be generated using the behavioral modeling options.
Model libraries
.LIB and .INC commands to search and insert
model definitions from model library files. Index search mode for fast
searches of multiple or large library files. Compatible with most component
vendor and third party model libraries. Includes extensive model libraries
of over 19,000 analog and digital (74, 74LS, 74ALS, 74AS, 74F, 74HC, 74AHC,
CD4000, ECL 10K, ECL 10HK series) parts, and vendor supplied models.
To view the complete list of models included, browse the Model Library Catalog file (library.txt 550KB). Or, download and install the Demo version. Then, open the "Model Library Database" icon in the TopSPICE folder, or select "Tools|Model libraries|Model Database" command from either the Schematic Editor or Circuit File Editor menu.
Other Features
Alphanumeric node names, global nodes, user defined
parameters and expressions, parameter passing to subcircuits, automatic
search of default model libraries, user definable default device models,
in-line and multiple comment line markers, simulation status display.
TopView is the graphical postprocessor program included with TopSPICE for plotting the simulation results and performing waveform analysis. To take full advantage of SPICE simulation results the user must be able to display the results graphically with a minimum of fuss. TopView allows quick and intuitive analysis of the output data in a manner similar as oscilloscopes are used to analyze real electronic circuits.
TopView was specifically designed for rapid viewing of the results for most typical design situations. Unlike other SPICE graphical postprocessor programs, which require the user to go through a cumbersome process of selecting waveforms and plot settings, TopView features fully automated plotting of simulation data. TopView's "Auto Plot" function will read a SPICE output file data, and it will automatically select the appropriate graph settings, assign different plot windows to different variable types such as voltages and currents, determine the units for labeling the axes and plot all the waveforms. To facilitate debugging or tracing of a circuit operation, TopView also includes a "Probe" mode which allows users to interactively pick and plot any waveforms from the simulation data.
Input Format: TopView accepts SPICE text output files in SPICE2G6 format (including HSPICE(tm), PSpice(tm) and SPICE3), TopSPICE binary output files, CSDF data files and user generated text data files.
Plots: Unlimited data points per waveform and unlimited number of waveforms (limited by available system resources) are supported. Data from multiple output files can be displayed on the same plot. Simultaneous display of analog and digital waveforms. Up to eight plots per graph.
Auto/Probe Plotting Modes: users can choose fully automated plotting of simulation results or manual selection of circuit variables. Fast automatic plotting with auto scaling, auto window selection, auto labeling. Auto/manual linear/log scaling of plots. X axis variable selection. Data can be shown as lines, symbols or bars.
Cursors: two cursors are available for reading out waveform values, calculating deltas and slopes, and placing labels anywhere on the plot area. Cursors can be used to find maximum, minimum, peak, RMS, etc. points on waveform. User selectable cursor shapes.
Zoom and scroll: users can zoom-in to any area of the plot, or manually set the axes limits. Then, the plot can be scrolled left-right or up-down.
Waveform operations: any arbitrary expression that can include waveform variable names, constants, arithmetic operator and math functions. Complex vector expressions. Also integration, differentiation and FFT analysis.
Post-processing: instant FFT, Smith charts, histogram plots, "eye" displays, tabulate variable & performance analysis functions.
Embedded commands: allows TopView postprocessor directive commands to be embedded in SPICE netlist files.
| Command | Description |
|---|---|
| #AUTOPLOT | Auto plot specified variables |
| #AUTOPLOT FFT | Calculate FFT and plot |
| #AUTOPLOT HISTOGRAM | Plot histogram |
| #AUTOPLOT SMITHCHART | Plot Smith chart |
| #CALC | Calculate expressions |
| #CALC FFT | Calculate FFT |
| #MEASURE DELAY | Measure delay |
| #MEASURE DELTA | Measure difference in Y values |
| #MEASURE FREQ | Measure frequency of periodic waveform |
| #MEASURE MAX | Measure maximum value |
| #MEASURE MIN | Measure minimum value |
| #MEASURE VALUE | Measure value of Y at specified X value |
| #MEASURE WIDTH | Measure X width (pulse, bandwidth, etc.) |
| #REVISION: | Circuit revision info |
| #SUBTITLE | Mark following line as the plot subtitle |
| #TABULATE | Tabulate variable |
Output: high quality output to printers. Graphic file export (WMF, EMF, BMP, PNG) option.
A graphical schematic entry program is included with TopSPICE. It allows the designer to draw electrical circuit schematics from which it generates complete SPICE netlist files automatically. It features:
Easy to use graphical user interface with on-line help facility. All commands are available through pull-down and pop-up menus and toolbar.
Includes symbols for all the SPICE circuit elements, TopSPICE model library parts and many other common components. Users can create and add new schematic symbols using a text editor or the symbol utility functions. Symbols from multiple symbol library files may be used on the same drawing.
Extensive symbol attributes options. Most symbols may be rotated, mirrored and/or flipped. No separate definitions are needed for each view. Option to draw symbols at twice normal size. Symbol "preview" box for quick part selection. Option to draw symbols at twice normal size.
Snap-to-grid, automatic part numbering and "double-click" to repeat part for fast placement of components.
"Auto-junction" and orthogonal drawing constraint modes for easy wiring connections.
Complete edit commands include cut, paste, copy, move, rotate, mirror, flip and change attributes. Double-click to edit any object attribute on the drawing. Edit operations can be applied to a group, area, subcircuit or entire schematic.
Advanced wire "rubberbanding" feature maintains both electrical connectivity and aesthetic appearance when moving parts on a schematic.
Node names may be given to wires and part pins by placing a label next to it. The assigned node name is used in the SPICE netlist file instead of a node number.
Easy schematic navigation with "auto-panning" and centering, position scroll bars, and multiple zoom levels and area zooming and many convenient keyboard shortcuts. Full page display option for any sheet size (A through E).
Support for schematic with multiple pages. A circuit schematic may be partitioned into a number of separate pages (up to 100).
Subcircuit (macromodel) support for hierarchical designs. The user has options to draw separate subcircuits on a schematic, use a macromodel in text (netlist) form, and write a SPICE .SUBCKT netlist of the entire schematic. Subcircuits can also be save as models to model and symbol libraries.
Auto symbol generator function automatically creates schematic symbols to match any subcircuit block.
Fast and user transparent generation of complete SPICE circuit files. SPICE commands, models, etc. may be included in a separate command file, which is automatically inserted to the SPICE netlist, or they may also be added directly on the schematic as text objects.
Option to show SPICE node numbers on schematic. Automatic connection of same name wires, pins, power rails and ground.
Full support for SPICE syntax including specification of device and source parameters, and subcircuits.
Support for TopSPICE digital functions and analog behavioral models.
DC operating point node voltages and source currents display on the schematic drawing.
Selection "disable" feature to remove temporarily components from the simulation circuit without modifying the schematic drawing for convenient debugging and design analysis.
"Auto save" feature automatically saves changes at user specified intervals.
User set configuration settings, zoom level and cursor position are saved and restored when editing the same schematic for quick design iterations.
Automatic updating of title block information.
High quality hard copy to most printers. Any sheet size may be printed on any paper size. Graphic file (WMF, EMF, BMP, PNG) export option.
PC with Pentium compatible or better CPU, 128MB RAM (for Windows XP systems, we recommend a minimum of 512MB for best performance), 200MB available hard disk drive space, CD-ROM drive, Windows 98/ME/2000/XP/Vista operating system.
Product specifications are subject to change without notice. All company and product names are trademarks or registered trademarks of their respective holders.
Copyright © 2007 Penzar Development.